CSPs are used in a wide variety of consumer electronics products. In particular, Wafer-Level CSP (WL-CSP)s are used in mobile phones, PDAs, lap top computers, printers and other applications. The WL-CSP integrated circuit (IC) is attached to a printed circuit board (PCB) by, for example, a conventional surface mount technology. The pads of the IC connect directly to the pads of the PCB through individual solder balls and thus do not require underfill encapsulation material.
The WL-CSP offers several advantages over other types of CSPs (e.g., ball grid array-type, laminate-type). The WL-CSP does not require bond wires or interposer connections between the IC and the solder balls. Since the WL-CSP IC pads connect directly to the PCB, the inductance between IC and the PCB is minimized thereby improving signal quality.
After a device having a WL-CSP attached to a PCB is built, the device is subjected to a drop test to measure its durability. The drop test is a technique for measuring the durability of a component by subjecting it to a free fall from a predetermined height onto a surface under prescribed conditions.
FIG. 1 illustrates a device 100 including a PCB 104 to which is attached a WL-CSP 108 by a plurality of solder balls 112. When subjected to a drop test, the device 100 is deformed due to the impact from a mechanical shock. FIGS. 2 and 3 illustrate the device 100 during a drop impact. As shown in FIGS. 2 and 3, depending on the orientation during the impact, the PCB 104 may be bent upward or downward. The WL-CSP 108 attached to the PCB 104 tends to follow the deformation of the PCB 104, which leads to uneven loading of the solder balls 212.
As WL-CSPs increase in complexity and functionality, the size of the silicon die (not shown) in the WL-CSP 108 and I/O count also increase. As the size of the silicon die (not shown) in the WL-CSP 108 increases, the solder balls at the periphery are subjected to increased loading and deformation because they are farther away from a neutral axis 216. An increase in the thickness of the silicon die (not shown) in the WL-CSP 108 also causes the WL-CSP 108 to become less compliant to bending, resulting in deformation.
The device 100 may also be subjected to a thermal cycle test, which is used to thermally cycle a semiconductor device between hot and cold temperatures to determine the durability of the device. FIG. 4 illustrates the effect on the device 100 during a thermal cycle test. Since the silicon die (not shown) in the WL-CSP 108 expands and contracts at a much lower rate than the PCB 104 during a thermal cycle test, the solder balls 112 at the periphery are subjected to high shear stress, hence resulting in poor test reliability.
Furthermore, a recent trend toward smaller bump pitch of the solder balls 112 has resulted in smaller diameter of the solder balls 112. A smaller bump pitch of the solder balls 112 also results in smaller Under Bump Metallurgy (UBM). Since the UBM opening defines the contact area of the solder balls 112 to the silicon die (not shown) in the WL-CSP 108, a smaller contact area lowers a threshold limit of the solder balls 112 to withstand shear and tensile loads during the drop test and the thermal cycling test.
Unlike a ball grid array (BGA) device that generally has some redundant solder balls as dummy balls to improve the BGA device's drop test and thermal cycling reliability, a WL-CSP device's solder balls are all functional because the WL-CSP device is not designed to accommodate high I/O counts like a BGA device. Consequently, the drop test and thermal cycle test performance of the WL-CSP device cannot generally be improved by adding redundant solder balls.